![]() ![]() So the latch will go to transparent mode and transmit an undefined state from Logic A through to Register B for a while. In Case B, the negative clock edge enables the latch before the arrival of the signal from logic A at the input of the latch. When Logic A is fast enough, no borrowing is necessary. We do not need to borrow any time to achieve our timing goal.įigure 3. In this case, the behavior of the latch is similar to that of a flipflop, and analysis is simple. In Case A, data arrives from logic A at Latch 2 before the falling edge of the clock at the Latch. Timing relationships set by the system clock. Depending on the delay incurred by the logic A in Path 1, we can have two scenarios of timing analysis that will decide the time we can borrow (Figures 3 and 4.)įigure 2. Let us examine this simple example to illustrate borrowing time to compensate for the delay through the logic cloud A. The figure 1 has 2 timing paths: Path 1 from the positive-triggered register (1) through logic A, to a negative-level latch (2), while Path 2 is from the latch, through logic cloud B, to a positive edge triggered register (3). ![]() A combinational path which is long enough and is determining the maximum frequency of the design can borrow some time from a shorter path in subsequent latch-to-latch stages to meet its timing (Figure 1.)įigure 1. Time borrowing technique can relax the normal edge-to-edge timing requirements of synchronous designs. A level-sensitive latch is transparent for the duration of an active clock pulse. The unique property which enables above advantages is time borrowing. Depending on the polarity of the enable input, we call latches positive-level or negative-level. ![]() The enabled state is also called transparent state. Flip FlopsĪ latch is a level-sensitive storage cell that is transparent to signals passing from the D input to output Q when enabled, and that holds the values of D on Q as of the time enable goes False. Finally, the paper will discuss challenges with latch-based design to hierarchical timing closure and partitioning, and some solutions. Third part of the paper will talk about the timing analysis complexities for latch-based design and how to deal with this complexity during the course of design. Next part describes some unique properties of latches that make them useful in high-frequency design. First part of the paper will discuss the advantages and disadvantages of latches compare to Flip-Flop. Latches and flip flops are the commonly used storage elements. Sequential circuits are the storage cells with outputs that reflect the past sequence of their input values, while output of the combinational circuits depends only on the present input. Digital blocks contain combinational and sequential circuits. ![]()
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |